8 Layer ENIG FR4 Via-In-Pad PCB
ʻO ka mea paʻakikī loa e hoʻomalu i ka lua plug i loko o ka via-in-pad, ʻo ia ka pōpō solder a i ʻole ka pā ma ka ʻīnika i loko o ka lua.Ma muli o ka pono o ka hoʻohana ʻana i ka BGA kiʻekiʻe kiʻekiʻe (ball grid array) a me ka miniaturization o SMD chip, ʻoi aku ka nui o ka hoʻohana ʻana i ka ʻenehana hole tray.Ma o ke kaʻina hana hoʻopiha hole, hiki ke hoʻohana ʻia ka ʻenehana hole i ka hoʻolālā a me ka hana ʻana i ka papa multilayer kiʻekiʻe, a pale i ka hoʻopili ʻana.Ua hoʻohana ʻo HUIHE Circuits i ka ʻenehana via-in-pad no nā makahiki he nui, a he hana kūpono a hilinaʻi hoʻi.
Nā ʻāpana o Via-In-Pad PCB
Nā huahana maʻamau | Nā huahana kūikawā | Nā huahana kūikawā | |
Kūlana hoʻopiha puka | IPC 4761 ʻAno VII | IPC 4761 ʻAno VII | - |
Min Hole Anawaena | 200µm | 150µm | 100µm |
Ka nui o ka papa liʻiliʻi | 400µm | 350µm | 300µm |
Anawaena Hole Max | 500µm | 400µm | - |
Nui pad kiʻekiʻe | 700µm | 600µm | - |
Piʻi kiʻekiʻe loa | 600µm | 550µm | 500µm |
ʻAspect Ratio: Maʻamau ma o | 1:12 | 1:12 | 1:10 |
ʻAspect Ratio: Makapō ma | 1:1 | 1:1 | 1:1 |
Hana o ka Puka Puka
1. Kāohi i ke kī mai ka hele ʻana ma ka puka hoʻokele ma ka ʻili o ka ʻāpana i ka wā e kūʻai aku ai
2.Avoid koena flux i loko o ka-puka
3. Kāohi i nā kini pōpopo mai ka puka ʻana i waho i ka wā e kūʻai ana i ka nalu, e hopena i ke kaapuni pōkole
4. Kāohi i ka paʻi solder ili mai ka kahe ʻana i loko o ka lua, e hana ai i ka wiliwili virtual a pili i ka pono
Pono o Via-In-Pad PCB
1.Improve wela wela
2. Ua hoʻomaikaʻi ʻia ka volta hiki ke kū i ka vias
3. Hāʻawi i kahi pālahalaha a kūlike
4.Lower parasitic inductance
Ko makou Pono
1. Own factory, hale hana 12000 square meters, hale hana kuai pololei
2. Hāʻawi ka hui kūʻai aku i ka wikiwiki a me ke kūlana kiʻekiʻe ma mua o ke kūʻai aku a ma hope o ke kūʻai aku
3.Process-e pili ana i ka ʻikepili hoʻolālā PCB e hōʻoia i hiki i nā mea kūʻai ke nānā a hōʻoia i ka manawa mua